Picture display device and method of driving the same

ABSTRACT

Disclosed is a high-definition liquid crystal display device wherein a video signal applied to the pixel electrode is compensated for a gain decrease in a high frequency range. A video signal processing circuit includes an inversion processing circuit which outputs at least one video signal inputted to a source driver circuit. The inversion processing circuit includes an amplifier and has function of amplification and inversion. A peaking processing circuit is connected to an amplifier in the inversion processing circuit. Even if a video signal frequency f vid  is in a high range of the amplifier, the amplifier gain is increased up to an middle range value (frequency range that the gain becomes constant). Because the peaking circuit compensates for characteristics of the liquid crystal panel, it is possible for the inversion processing circuit to apply an alternating current signal reproduced with fidelity of a potential determined by a correction circuit to the liquid crystal cell.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to active matrix liquid crystaldisplay devices incorporating therein driver circuits, and moreparticularly to a technology to enhance definition and image quality forthe liquid crystal display devices.

[0003] 2. Description of Related Art

[0004] In recent years, technological developments have being putforwarded in flat panels, such as liquid crystal displays (LCD), plasmadisplay panels (PDP), electroluminescence (EL) displays, as cathode raytubes (CRT) replacing displays. Among these flat displays, liquidcrystal displays are the largest in marketplace and utilized for variousdisplay mediums including notebook personal computers, digital cameraswith liquid crystal panels, car navigation systems, projectors and widescreen televisions.

[0005] The advantage of the liquid crystal display greater than the CRTlies in that the display area is obtained wide due to display sectionflatness and high definition given by the dot matrix display scheme.

[0006] The high definition is meant to increase in the number of pixelsin the liquid crystal display. A drive frequency increases with increasein the number of pixels. For example, the number of pixels, althoughabout four hundreds of thousands in NTSC rating, mounts to approximatelytwo millions (1920×1080 pixels), in HDTV rating. Accordingly, in HDTVrating the input video signal has its maximum frequency reaching as highas 20 to 30 MHz, despite it was 6 MHz in the NTSC rating.

[0007] In order to display video signals with accuracy, a clock signalrequires a frequency of several times (e.g., about 50 to 60 MHz) that ofthe video signal. It is expected that display with higher definition andimage quality be furthermore required from now on and video signals witha dot clock extremely high in speed be dealt with.

[0008]FIG. 11A shows a simplified routes for video signals to beinputted to the conventional liquid crystal display panel. The liquidcrystal display panel 10 is arranged, as shown in FIG. 11A, with a pixelmatrix area 11, and a gate driver circuit 12 and a source driver circuit13. The gate driver circuit 12 is also called a scanning line drivercircuit. The source driver circuit 13 is also called a signal linedriver circuit or a data line driver circuit. The pixel matrix area 11has pixels, each pixels having a liquid crystal cell 15 and a pixel TFT16. The liquid crystal cell 15 possesses a capacitor structure havingdielectric sandwiched between a pixel electrode to be inputted by avideo signal and an opposite electrode. The pixel TFT 16 includes a gateelectrode, a source electrode and a drain electrode. The gate electrodeis connected to a scanning line 17, the source electrode (or the drainelectrode) is connected to a signal line 18 and the drain electrode (orthe source electrode) is connected to the pixel electrode of the liquidcrystal cell 15. The scanning line 17 is connected to the gate drivercircuit 12 and the signal line 18 is connected to the source drivercircuit 13. The scanning line 17 is also called a gate line. The signalline 18 is also called a data line, a source line or a drain line.

[0009] The video signal to be applied to the pixel cell is processedsuitably for display characteristics of the liquid crystal panel 10 bythe video signal processing circuit 20. The video signal processingcircuit 20 mainly performs gamma correction, alternation andamplification to process on video signals inputted from the outside. Theprocessed video signal is inputted from the source driver circuit 13through the signal line 18 to the pixel matrix area 11, thus applied tothe pixel electrode of the liquid crystal cell 15. The liquid crystalmaterial in the liquid crystal cell 15 varies in light transmission ratedepending upon a voltage applied to. The change of light transmissionrate corresponds to tone whereby images are formed by the entire liquidcrystal cells 15.

[0010] In order to realize high quality display on the liquid crystalpanel, the video signal processing circuit 20 requires an amplifier 21(see FIG. 11B) to amplify signal waveforms with fidelity. This isbecause the amplifier 21 is at a final output end of the video signalprocessing circuit 20 where the video signal to be applied to the pixelelectrode of the liquid crystal cell 15 is finally determined inamplitude and form. The video signal applied to the pixel electrode is apulse-formed signal. Consequently, the amplifier 21 is required not tocause pulse signal amplitude deterioration and rounding of pulsewaveforms.

[0011] It is known that the amplifier 21 generally has a frequencycharacteristic as shown in numeral 1101 of FIG. 11C wherein a voltagegain is nearly constant in a middle range but, in a range exceeding acertain frequency, decreases at a constant rate. The decrease rate is−20 dB/decade (−6 dB/octave) where the amplifier is in one stage. Thecause of decreasing the gain in the higher range is due to outputimpedance increase in the single amplifier.

[0012] In the liquid crystal display, however, consideration has to begiven not only to the output end voltage of the amplifier 21 but also tothe voltage finally applied to the pixel electrode. Accordingly, thereis a necessity for the frequency characteristic of the amplifier 21 inthe video signal processing circuit to consider also the resistance RLCand capacitance CLC connected between the amplifier 21 and the liquidcrystal cell 15 instead of the single amplifier 21. Thereupon, as shownin numeral 1102 of the FIG. 11C the frequency range in which the gain ofthe pixel electrode of the liquid crystal cell 15 begins to lower isshifted to a lower side than the gain of the single amplifier 21 byimpedance decrease due to the liquid crystal panel resistance RLC andcapacitance CLC.

[0013] The increase of definition in the liquid crystal display is pixeland pixel density increase. The pixels, if increased, increases thenumber of connection lines, increasing liquid panel resistance RLC. Thedensity increase actualizes the problem of pixel matrix parasiticcapacitance, giving rise to a tendency of increasing the capacitanceCLC. Accordingly, the increase of definition results in a shift of thefrequency range in which the gain of the amplifier 21 is flat toward thelower range side. In order to avoid the gain decrease, the resistanceRLC may be decreased. In order to reduce the resistance RLC, thethickness of interconnection may be increased. However, the increase ininterconnection thickness leads to increase in interconnect occupationarea, running counter to a direction of a technological developmentcalled pixel shrinkage.

[0014] The increase in definition also requires high frequency drive.The video signal drive frequency in the HDTV rating requires as high as20 to 30 MHz. If an HDTV rating display is realized by a liquid crystalpanel, the video signal frequency f_(vid) unavoidably comes to afrequency range that the gain on the pixel electrode is decreased due tothe above-described increase in definition of the liquid crystal panel.

[0015] If a gain decrease on the pixel electrode occurs in the videosignal frequency f_(vid), the video signal decreases in black or whitelevel, resulting in image graying (muddy color in color display) andhence degradation in display quality.

[0016] High frequency drive has been unnecessary for such a VGA or SVGArated liquid crystal panel as having the horizontal number of pixels ofless than a thousand. Consequently, even if there has been a decrease onthe high frequency side in the gain of the voltage applied to the pixelelectrode, the amplifier 21 could be used at a frequency at which thegain is flat. The problem of the gain decrease concerning the frequencyhas not been recognized at all.

SUMMARY OF THE INVENTION

[0017] It is an object of the present invention to provide a liquidcrystal display device which is capable of displaying with high quality,wherein the gain reduction in the high frequency range is compensatedfor the video signal to be applied to pixel electrodes of a pixel matrixarea to eliminate the above-described problem due to increase indefinition for the display device.

[0018] According to a structure of the present invention, a liquidcrystal display device, at least comprises: a pixel matrix area having aswitching element for each pixel electrode; a first driver circuitconnected to scanning lines -of the pixel matrix area; a second drivercircuit connected to signal lines of the pixel matrix area; a videosignal processing circuit for alternating video signals and outputting aplurality of alternating video signals onto the first driver circuit;and a control circuit for creating control signals to control on driveto the first driver circuit, the second driver circuit and the videosignal processing circuit; wherein the video signal processing circuithas a circuit for effecting a peaking process connected to an output ofan amplifier placed at the closest to each output terminal outputtingthe alternating current video signals.

[0019] According to another structure of the invention, the video signalprocessing circuit converts the video signals into alternating currentvideo signal and outputs the alternating current video signals to thefirst driver circuit. The alternating current signals are constituted bytwo kind of alternating current signals in an inverted relation to eachother. The video signal processing circuit has a circuit for effecting apeaking process connected to an output of an amplifier placed at theclosest to each output terminal outputting the alternating current videosignals.

[0020] In the liquid crystal display device of the invention, a peakingprocessing circuit is connected to an output of the amplifier placed atthe closest to an output terminal outputting the video signals. Thismakes it possible to display in high definition display by compensatingfor voltage gain on the pixel electrodes due to reduction in impedanceloaded on the amplifier, i.e., impedance of the pixel matrix area ordriver circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0021]FIG. 1 is a block diagram showing a constitution of a liquidcrystal display device according to the present invention;

[0022]FIG. 2 is a partial block diagram showing a constitution of aninversion processing circuit;

[0023]FIG. 3 is a diagram showing a frequency characteristic of anamplifier in the inversion processing circuit in FIG. 2;

[0024]FIG. 4 is a partial block diagram showing a constitution of theinversion processing circuit, which is a modification of FIG. 2;

[0025]FIG. 5 is a block diagram showing a constitution of the liquidcrystal display device of Embodiment 1;

[0026]FIG. 6 is a partial diagram including a source driver circuit andpixel matrix area of Embodiment 1;

[0027]FIG. 7 is signal waveforms showing a synchronization signal, apolarity inversion signal, an input video signal and a first and asecond alternating current video signal of Embodiment 1;

[0028]FIG. 8 is a timing chart on signals in the source driver circuitof Embodiment 1;

[0029]FIG. 9 is a partial diagram including a source driver circuit anda pixel matrix area of Embodiment 3;

[0030]FIG. 10 is a schematic structural view of a rear projector typedisplay device of Embodiment 4;

[0031]FIGS. 11A, 11B and 11C are prior art explanatory views.

DETAILED DESCRIPTION OF THE INVENTION

[0032] The invention will now be described with reference to FIG. 1through FIG. 4.

[0033] Referring first to FIG. 1, there is shown a block diagram of aliquid crystal display device according to the present invention. Theliquid crystal display device includes a liquid crystal panel 100 todisplay images, a video signal processing circuit 110 to render an inputvideo signal into an alternating current form, and a control circuit 120to control the liquid crystal panel 100 as well as video signaloperation timing.

[0034] In the liquid crystal panel 100, a pixel matrix area 101 isconnected with a source driver circuit (a signal line driver circuit)103 through a plurality of signal lines 102 vertically extending inparallel with each other, and with a gate driver circuit (a scanningline driver circuit) 105 through a plurality of scanning lines 104horizontally extending in parallel with each other.

[0035] The pixel matrix area 101 is formed, on a pixel-by-pixel basis,with TFTs (thin film transistors) 106 as switch elements each arrangedclose to an intersection of a signal line 102 and a scanning line 104and a liquid crystal cell 107 connected to the TFT 106. The scanningline 104 is connected at its one end to a gate electrode of acorresponding TFT, while the signal line 102 is connected at its one endto a source electrode or a drain electrode of the TFT. The liquidcrystal cell 107 is formed with a capacitor by a pixel electrode, anopposite electrode and a liquid crystal material sandwiched between thepixel electrode and the opposite electrode. The opposite electrode ismade common for all the liquid crystal cells 107, and has its potentialheld at a common potential (center potential).

[0036] The driver circuits 103, 105 are formed by TFTs and so on.Polycrystalline silicon films crystallized from amorphous silicon filmsare suitably employed for the TFTs of the driver circuits 103, 105 andTFT 106 in view of a field effect mobility. It is also possible to use afilm crystallized from an amorphous silicon-germanium film.

[0037] The video signal processing circuit 110, the control circuit 120,etc. are mounted on a different substrate from the liquid crystal panel100, e.g., on another printed substrate. The circuits on that substrateand the circuits on the liquid crystal panel 100 are connected throughcables, flexible circuit boards, or the like. Incidentally it isneedless to say that it is preferred in view of integration to arrange apart or the entire of a peripheral circuit including the video signalprocessing circuit 110 and the control circuit 120 on the same substrateas the liquid crystal panel.

[0038] The video signal processing circuit 110 has an A/D(analog/digital) converter 111, a correction circuit 112, a D/A(digital/analog) converter 113 and an inversion processing circuit 114.The control circuit 120 is a circuit to create pulses (start pulse,clock pulse, synchronous signal, polarity inversion signal, etc.) forcontrolling timing to operate the source driver circuit 103, the gatedriver circuit 105, the video signal processing circuit 110, and so onbased on the synchronization signal 200.

[0039] The source driver circuit 103 is inputted by a video signalhaving been rendered in an alternating current form by the video signalprocessing circuit 110, a start pulse signal, clock signal, horizontalsynchronization signal, etc. from the control circuit 120. The operationof the liquid crystal display device in the present embodiment isexplained below.

[0040] The control circuit 120 repeats an operation (frequencydivisions) to count a clock with a previously set count number(frequency division ratio) on an synchronized oscillation clock signal(OSC) as a source oscillation outputted from an oscillatorphase-synchronized, on the basis of an input synchronous signal 200 as areference. Simultaneously with this frequency division, the clock iscounted to create a start pulse (SPD) 201 in a screen horizontaldirection, a start pulse (SPS) 202 in a screen vertical direction, aclock pulse (CLD) 203 in the screen horizontal direction, a clock pulse(CLS) 204 in the screen vertical direction, and a polarity reversalsignal (FRP) 205. Further, there are cases to create a horizontalsynchronization signal (HSY) and a vertical synchronization signal(VSY), wherein HSY and VSY are used as a reference in a horizontal orvertical direction for displaying characters on the screen.

[0041] The input video signal 210 to be inputted from the outside of thedisplay device is an RGB analog signal having a video data pair of red(R), green (G) and blue (B) for each pixel unit, which is transferred tothe video signal processing circuit 110 every unit time. The input videosignal 210 is also a continuous signal continuous in the vertical numberof lines, which has one screen (one frame) video signal divided by thenumber of lines in the vertical direction.

[0042] Correspondingly to the input video signal 210, the pixel matrixarea 101 has R, G and B pixels which are repeatedly placed in the orderin the horizontal direction correspondingly to different three colors ofred, green and blue, thereby vertically constituting a pixel array. Forexample, if the pixel matrix area 101 is considered to be configured byhorizontally 1024 pixels and vertically 768 pixels, then one screenvideo signal be formed by a continuous signal having, in the verticalnumber (768 columns) of lines, horizontal lines each includinghorizontally 1024 pixel information signals. In usual cases, the inputvideo signal 210 is a signal corresponding to a CRT, but not suited fora liquid crystal panel. Due to this, the video signal processing circuit110 performs various signal processing on the input video signal 210.

[0043] In the video signal processing circuit 110, the input videosignal 210 is converted into a digital RGB signal by an A/D converter111 and outputted to the correction circuit 112. In the correctioncircuit 112, the video signal in the digital signal form is subjected togamma correction and the like regarding the characteristic of a liquidcrystal material thus being improved in tone characteristic. Thecorrected video signal is again converted into an analog RGB signal bythe D/A converter 113.

[0044] To digitize the video signal 210 by the A/D converter 111 is dueto enabling the correction with easiness and accuracy by the correctioncircuit 112. Note that the A/D converter 111 can be omitted in the caseof the input video signal 210 be a digital signal.

[0045] The corrected video signal is then amplified to a potentialsuited for the liquid crystal panel (generally, −5V to 5V) by theinversion processing circuit 114. That is, the corrected video signal ismade into an alternating current form by reversing its polarityaccordingly to a pulse potential of polarity reversal signal (FRP) 205inputted from the control circuit 120 to the inversion processingcircuit 114.

[0046] The source driver circuit 103 for the liquid crystal panel 100 isinputted by SPD 201 and CLD 203 created by the control circuit 120,together with the video signal 211 in the alternating current form. TheSPD 201 is a pulse signal to define in which timing of one horizontaltime period display is to start. The CLD 203 is a pulse signalcorresponding to each pixel in the horizontal direction. According tothis signal, the source driver circuit 103 performs sampling on thevideo signal 211 in the alternating current form and then outputs avoltage (video signal) corresponding to each pixel onto the signal line102.

[0047] The gate driver circuit 105 is inputted by the SPS 202 and CLS204 created by the control circuit 120. The SPS 202 is a pulse signal todefine in which timing of one vertical time period display is to start.The CLS 204 is a pulse signal corresponding to each pixel in thevertical direction. The gate driver circuit 105 selects, every onehorizontal period, a scanning line 104 to the pixel matrix area 101 inan order from above, thus displaying images.

[0048] The inversion processing circuit 114 of the video signalprocessing circuit 110 is a circuit to perform amplification andinversion processing, which is basically configured by an amplifier. Asshown in the conventional example (see FIG. 11C), amplifier has acharacteristic that on a high range side the voltage gain decreases withincrease in the frequency. If the frequency f_(vid) of a video signal tobe processed is higher than 20 MHz, the gain is decreased in the signalapplied to a pixel electrode of the liquid crystal cell 107 even at sucha frequency that the gain is constant in the amplifier of the inversionprocessing circuit 114. Because, resistors or capacitors are existed inthe liquid crystal panel 100 connected to the output of the inversionprocessing circuit 114. This makes it impossible to apply the data ofthe digital video signal having been corrected by the correction circuit112 to the pixel electrode with fidelity.

[0049] For high quality display, the alternating current video signal211 applied to the pixel electrode of the liquid crystal cell 107requires reproduction with fidelity on the input video signal 210. Also,because the alternating current video signal 211, if inputted to thesource driver circuit 103, is divided by signal lines 102, thecorrection to the entire alternating current video signal 211 is carriedout by the video signal processing circuit 110. Consequently, thecorrection to a voltage gain in the pixel electrode is also conducted bythe video signal processing circuit 110 as a prior stage to the sourcedriver circuit 103. It is preferred in the video signal processingcircuit 110 to compensate for decreasing of the voltage gain in thevoltage to be applied to the pixel electrode by a circuit as close aspossible to the liquid crystal cell 107. In the present invention, theoutput signal of the inversion processing circuit 114 to be finallyinputted to the liquid crystal panel is the video signal 211, andaccordingly the inversion processing circuit 114 is a closest amplifierto an output end of the alternating current video signal 211.

[0050] In order to compensate for decreasing of the gain in the liquidcrystal cell 107, a peaking processing circuit 117 is connected to theoutput of an amplifier 115 of the inversion processing circuit 114 tocarry out a peaking process, as shown in FIG. 2. FIG. 3 shows therelation between frequency and voltage gain with regard to thealternating current video signal applied to a pixel electrode. In thecase of the peaking processing circuit 117 is not connected as shown inthe numeral 31 of the FIG. 3, the voltage gain of the signal at thevideo signal frequency f_(vid) applied to the pixel electrode of theliquid crystal cell 107 is decreased. In the case of the peakingprocessing circuit 117 is connected to the output of the amplifier 115as shown in the numeral 32 of the FIG. 3, the voltage gain of the signalat the video signal frequency f_(vid) applied to the pixel electrode isincreased up to a gain in a middle range (the frequency range constantin gain). Incidentally, the characteristic of the peaking processingcircuit 117 was determined to compensate for the decrease of the voltagedue to load impedance (the impedance possessed by the liquid crystalpanel 100) by the amplifier 115.

[0051] The peaking processing circuit 117 is a means to compensate forthe characteristic of the liquid crystal panel 100, wherein it is mostimportant to connect it to the amplifier 115 positioned closest to theoutput terminal of the video signal processing circuit 110. Byconnecting the peaking processing circuit 117 to the output of theamplifier 115, the alternating current video signal corrected by thepeaking processing circuit 117 can be inputted to the source drivercircuit 113 with possibly reduced disturbance. Due to this, it becomespossible to apply with fidelity an alternating current video signal 211reproduced of a potential determined by the correction circuit 112 tothe pixel electrode of the liquid crystal cell 107.

[0052] Also, even if a feedback circuit is provided at the output of theamplifier 125 of the inversion processing circuit 124 and the feedbackcircuit is configured by a peaking processing circuit as shown in FIG.4, it is possible to obtain the same effect as the inversion processingcircuit 114 of the FIG. 2. In the FIG. 4, same reference numerals denotesame constituent components. The FIG. 4 is a modification of theinversion processing circuit 114 of the FIG. 2.

[0053] In order to improve the decrease of the gain on a high range sideof the applied voltage to the pixel electrode, devising is required toreduce the resistance or capacitance in the liquid crystal panel 100.However, it is quite difficult in a highly definition panel havingpixels vertically in number exceeding one thousand to improve thedecrease of the gain through panel design or manufacture technology.Although interconnections requires low resistance material selection,interconnect width increase and so on, they are difficult to practicallyapply due to the pixel shrinkage and processing problems as statedbefore thus resulting in deterioration in display characteristics.Accordingly, the problem of the gain decrease is quite difficult toeliminate by the liquid crystal panel design or process technologyimprovement. Meanwhile, the problem of the gain decrease can be easilydissolved by the peaking processing circuit 117 of the presentinvention.

[0054] The gain decrease in the video signal was improved herein byconnecting the peaking processing circuit 117 to an output terminal ofthe video signal processing circuit 110. Amplitude decrease and pulsewaveform rounding are caused in start pulse or clock pulse signals dueto liquid crystal panel characteristics. Such amplitude decrease andpulse waveform rounding of the pulse signal can be prevented byconnecting the peaking processing circuit also to an amplifier connectedto an output end of the liquid crystal panel 100 of the control circuit120, or an amplifier closest to an output end of a start pulse signal202, 201 or clock pulse signal 203, 204, as shown in the FIG. 2 and theFIG. 4.

[0055] For example, where in the liquid crystal panel 100 the pixel TFTs106 for the pixel matrix area 101 are varied in threshold from pixel topixel, the pixel TFTs 106 are different in turning-on voltage. If thepulse waveform becomes round, inclination is caused in thesignal-waveform rise portion. Accordingly, if there is variation inthreshold voltage, the timing of turning on the TFTs deviates therebyputting image display timing out of order.

[0056] On the other hand, if the pulse signal is in rectangular, theTFTs are brought into coincidence in the timing of turning on even ifthere are somewhat variations in TFT threshold voltage. By preventingthe pulse waveform from rounding by the provision of the peakingprocessing circuit 117, it is possible to relax the threshold voltagecharacteristics required for the TFTs in the liquid crystal panel 100and hence reduce the number of liquid crystal panels having poorconditions.

[0057] Embodiments of the present invention are described using FIG. 5to FIG. 10.

[0058] [Embodiment 1]

[0059] Referring to FIG. 5, there is illustrated a block diagram showinga constitution of the liquid crystal display device according to thepresent embodiment. The liquid crystal display device comprises a liquidcrystal panel 300 of a type integral with peripheral driver circuits, avideo signal processing circuit 310 and a control circuit 320.

[0060] Here, the video signal processing circuit 310, the controlcircuit 320, etc. are mounted on a different substrate from the liquidcrystal panel 300, e.g., on a printed substrate. The different substrateand the liquid crystal panel 300 are connected by cables, flexiblecircuit boards, or the like. Incidentally, it is needless to say that itis preferred from a integration view point to structure a part or theentire of peripheral circuits including the video signal processingcircuit 310 and the control circuit 320 on the same substrate as theliquid crystal panel.

[0061] The liquid crystal panel 300 has a pixel matrix area 301 having aplurality of scanning lines 302 horizontally extending in parallel witheach other and a plurality of signal lines 303 vertically extending inparallel with each other and perpendicular to the scanning lines 302.The scanning lines 302 are connected to a gate driver circuit 304, whilethe signal lines 303 are connected to a source driver circuit 305.

[0062] The pixel matrix area 301 is formed, on a pixel-by-pixel basis,with thin film transistors 306. Each of the thin film transistors 306 isarranged close to an intersection of the scanning line 302 and thesignal line 303 and liquid crystal cell 307 connected to each of thethin film transistors 306. The thin film transistors 306 are utilized asswitch elements. The gate driver circuit 304 and the source drivercircuit 305 include thin film transistors. The thin film transistorsconstituting for the pixel matrix area 301, the gate driver circuit 303and the source driver circuit 305 are formed by using a polycrystallinesilicon films or the like as a semiconductor material. Thepolycrystalline silicon film was obtained by heating an amorphoussilicon film formed on a quartz substrate to which nickel was added forthe purpose of promoting crystallization of the amorphous silicon,according to a technology described in Japanese laid-open patentpublication No. 8-78329 (the laid-open date is Mar. 22, 1996), an entiredisclosure of which is incorporated herein by reference. Thus, thin filmtransistors were formed based on the technology of the patentpublication. The semiconductor material has no especial limitationprovided that having a crystallinity and good field effect mobility. Itis possible to use a film obtained by crystallizing an amorphousgermanium-silicon film.

[0063] The liquid crystal cell 307 has a capacitor structure formed by apixel electrode connected to the drain (or the source) of the TFT 306,an opposite electrode and a liquid crystal material sandwiched betweenthe pixel electrode and the opposite electrode. The opposite electrodeis common to the liquid crystal cells of all pixels and have a commonpotential (center potential).

[0064] The scanning line 302 has one end connected to the gate electrodeof a corresponding TFT and the other end connected to the gate drivercircuit 304. Also, the signal line 303 has one end connected to thesource electrode of the TFT and the other end connected to the sourcedriver circuit 305.

[0065] It should be noted that although in FIG. 5 the signal lines 303are depicted in a not-many number, they practically in the same numberas the number of pixel electrodes in the horizontal direction of thepixel matrix area 301. Similarly, the scanning lines 302 are in the samenumber as the number of pixel electrodes in the vertical direction ofthe pixel matrix area 301.

[0066] The control circuit 320 creates and outputs pulse signalsrequired to drive the liquid crystal panel (start pulse, clock pulse,synchronous signal, polarity reversal signal, etc.) based on an inputsynchronization signal 400. The source driver circuit 305 is inputted byfirst and second SPD 401, 402 and first and second CLD 403, 404. Thegate driver circuit 304 is inputted by SPS 405 and CLS 406. The videosignal processing circuit 310 is inputted by FRP 407.

[0067] The video signal processing circuit 310 processes an input videosignal 410 and output a first alternating current video signal 411 andsecond alternating current video signal 412 to the source driver circuit305. There are illustrated in FIG. 7 signal waveforms as an example ofan input video signal 410, synchronization signal 400, polarity reversalsignal (FRP) 407, first alternating current video signal 411 and secondalternating current video signal 412.

[0068] The video signal processing circuit 310 in this embodiment has anA/D converter 311 and a correction circuit 312. The correction circuit312 has two line systems of video signal output lines wherein the outputsignal lines are respectively connected with D/A converters 313, 314.The D/A converters 313, 314 has their outputs respectively connectedwith amplifying circuits 315, 316.

[0069] The video signal processing circuit 310 is inputted by an inputvideo signal 410 that is an analog signal of RGB. In the A/D converter311, an input video signal 410 is converted into a digital signal thatis easy to perform signal correction. The input video signal may employa digital RGB signal in place of an analog RGB signal. In such a case,the A/D converter 311 is unnecessary.

[0070] The digitized video signal is inputted to the correction circuit312. In the correction circuit 312, the input video signal (digitalsignal) is subjected to various corrections by arithmetic operations. Inprincipal gamma correction is carried out for conversion into a signalsuited for display on the liquid crystal panel. The gamma-correctedsignal is divided into two digital signals of first and second correctedsignals 413, 414 to be outputted.

[0071] The first and second corrected signals 413, 414 are created suchthat they become alternating current signals with a polarity-reversedrelation, when the first and second corrected signals 413, 414 areconverted into analog signals. The changing of signals into thealternating current signals is performed based on the timing of FRP 407created by the control circuit 320. Meanwhile, it is preferred that thecorrection circuit 312 is configured with a memory circuit totemporarily memorize an input signal and a signal delay circuit tocorrect a phase shift caused by dividing into two signals.

[0072] The corrected signals 413, 414 outputted from the correctioncircuit 312 are respectively inputted to the D/A converter 313, 314where they are converted into analog signals. These analog signals arein a relation that they are made in alternating current forms and thatthe polality are reversed each other. These two signals are created bythe correction circuit 312 such that the output analog signals of theD/A converters 313, 314 are in an inverted relation in polarity.

[0073] The first corrected signal 413 and the second corrected signal414 outputted from the correction circuit 312 are respectively convertedinto analog signals by the corresponding D/A converters 313, 314. Theanalog signals outputted from the D/A converters 313, 314 are inputtedto amplifying circuits 315, 316. In the amplifying circuits 315, 316,the input analog signals are amplified in voltage value to a magnitudesuited for the liquid crystal panel (−5V to 5V) and outputted as firstand second alternating current video signals 411, 412 to the sourcedriver circuit 305.

[0074] In the signal processing circuit 310, the two amplifying circuits315, 316 are in a final output stage to the source driver circuit 305.Similarly to FIG. 2, in this embodiment, respective peaking processingcircuits are connected to output terminals of the amplifying circuits315, 316. With such a structure, the corrected signals by the correctioncircuit 312 can be reproduced with fidelity into first and secondalternating current video signals 411, 412 as analog signals, givingpossible high quality and high image quality display. Incidentally,feedback circuits may be connected to outputs of the amplifying circuits315, 316 to configure the feedback circuits by peaking processingcircuits as shown in FIG. 4.

[0075] In the present embodiment, the two D/A converters and the twoamplifying circuits were used in number corresponding to the two signallines in order to prevent a phase shift between the first and secondalternating current video signals 411, 412 from occurring. However, thenumber of the D/A converter and amplifying circuits may be 2n (n is apositive number) so long as being allowed in circuit arrangement.

[0076] The two alternating current video signals 411, 412 thus obtainedare inputted to the source driver circuit. This makes it possible todecrease the operating frequency of the shift register to a half ascompared with a case inputting one signal to the source driver circuit.

[0077] In the present embodiment, in the amplifying circuit 315, 316 asshown in FIG. 2, a peaking processing circuit is connected to anamplifier closest to its output terminal. With this structure, it ispossible to compensate for decrease of the gain in the alternatingcurrent video signals 411, 412 at the pixel electrode. Also, byinputting to the source driver circuit 305 the two alternating currentvideo signals 411, 412 that have the same image information (the samevoltage) and are in an inverted relation in polarity, the invertedperiod can be reduced in the alternating current video signals 411, 412and the video signals 411, 412 can be prevented from causing a phaseshift or noise, enabling high quality display.

[0078] The method for driving the liquid crystal panel is explainedhereinbelow using FIG. 6 to FIG. 8 together with FIG. 5.

[0079] The gate driver circuit 304 includes a vertical shift registercontrollable of scan direction, a level shifter to convert an outputsignal of the shift register into a required voltage, an output buffercircuit and so on. The output buffer circuit in the present embodimentis a circuit to amplify or impedance-convert a held voltage to apply itto the display section. Various circuits including an inverter as atypical configuration may be considered.

[0080] The source driver circuit 305 includes a two-phase horizontalshift register controllable of scanning direction and a sampling circuitfor sampling video signals to drive the pixel portions. The samplingcircuit is configured by a plurality of switching TFTs and a capacitor.FIG. 6 shows a circuit diagram of a source driver circuit 305 and pixelmatrix area.

[0081] The source driver circuit 305, as shown in FIG. 6, can beconfigured by various circuits including a typical configuration of ashift register, level shifter, switch, inverter, output buffer circuitand so on. This is not limited to the present embodiment configurationprovided that it is a circuit to sample and apply video signals to thedisplay section. It should be noted that the signal lines are in thesame number as the number of horizontal pixel electrodes of the liquidcrystal panel. Similarly, the number of scanning lines is the same asthe number of vertical pixel electrodes.

[0082]FIG. 7 shows a signal waveforms of the synchronization signal 400,FRP 407, input video signal 410, and the first and second alternatingcurrent video signals 411, 412 as outputs of the video signal processingcircuit 310.

[0083]FIG. 8 shows a timing chart for the source driver circuit 305. Thesource driver circuit 305 is inputted by two video signals from thevideo signal processing circuit 310, and a start pulse signal, clocksignal, horizontal synchronization signal, etc. from the control circuit320.

[0084] The input video signal 410 is subjected to various corrections(liquid crystal display gamma correction, camera gamma correction,corrections suited for user's requirement, etc.) in the video signalprocessing circuit 310, outputting alternating current video signals411, 412. As shown in FIG. 7, FRP 407 is inverted in polarity everyframe. The alternating current video signals 411, 412 are alternatingcurrent signals having a center potential as a reference, which have asame inversion period of every 1 frame as FRP 407. The alternatingcurrent video signals 411, 412 are signals having respective potentialsthat are symmetric with respect to the center potential, being signalsin an inverted relation in polarity to each other.

[0085] The input video signal 410 herein was substantially made into analternating current form by the correction circuit of the video signalprocessing circuit 310, i.e. making into the alternating current formwas by processing a digital signal. It can be easily understood that thetwo alternating current video signals 411, 412 can be in an invertedrelation in polarity to each other even by making into an alternatingcurrent form after converting into analog by the D/A converters 313,314. Making a digital signal into an alternating current form can reducethe burden on the amplifying circuits 415, 416 as compared with makingan analog signal into an alternating current form.

[0086] The first and second alternating current video signals 411, 412are respectively inputted to the sampling circuits of the source drivercircuit 305. In a first shift register section, a first alternatingcurrent video signal 411 sampled by the sampling circuit is outputtedonto an odd-numbered signal line, according to CLD 403 and SPD 401. In asecond horizontal shift register section 308, a second alternatingcurrent video signal 412 sampled by the sampling circuit is outputtedonto an even-numbered signal line, according to inputted second SPD 402and second CLD 404.

[0087] Where providing the two-phase shift register sections 308 and309, the shift-register operational frequency can be reduced to a half(½) as compared with a case using only one of shift registers as clearfrom a waveform diagram in FIG. 7.

[0088] Although the present embodiment showed the example that an analogvideo signal was divided into two, the signal even if divided into n (nis an even number) may be applied to the present invention. With such astructure, the video signal can be further reduced in frequency. Wherethe alternating current signal is n divided, an n-phase shift registersmay be employed. This results reducing the shift-register operationalfrequency to 1/n as compared with a case using only one of shiftregisters.

[0089] The operation of pixels applied by first and second alternatingcurrent video signals 411, 412 is explained with reference to FIG. 6showing one example of peripheral circuits of the source driver circuit305.

[0090] If a signal voltage is applied only to a scanning line (TFT closeto an intersection is turned on), pixel TFTs are turned on. A firstalternating current video signal 411 is applied onto a signal line 1 insynchronism with the scanning signal. A positive signal is applied to apixel electrode Al connected to the odd-numbered signal line 1.

[0091] Similarly, a second alternating current video signal 412 is thenapplied to a signal line 2 in synchronism with the scanning signal. Anegative signal is applied to a pixel electrode A2 connected to theeven-numbered signal line 2.

[0092] By the repetition of this operation, positive signals are appliedin order to pixel electrodes (A1, B1, C1 and A3, B3, C3), while negativesignals are applied to pixel electrodes (A2, B2, C2 and A4, B4, C4).

[0093] After 1-frame period, when a signal voltage is again applied tothe scanning line A (TFT close to an intersection is turned on), thefirst alternating current video signal 411 and the second alternatingcurrent video signal 412 are inverted in polarity as shown in FIG. 7,the polarity of the signal applied to the pixel electrode is reversed.By repeating the operation, the amount of transmission light through theliquid crystal varies depending on the potential of the pixel electrode,whereby the pixels as a whole display an image.

[0094] In this manner, source line inversion drive is conducted. In thepresent embodiment, alternating drive (source line inversion) can beperformed by using video signals that are polarity-inverted only everyscreen. That is, with the alternating drive method in the presentembodiment, the inverted period of the video signal upon source lineinversion drive display is greatly increased from a conventionalone-pixel write period to the one-screen write period. Due to this, thesignal processing circuit and the source driver circuit are reduced inpower consumption and decreased in phase shift and noise problem.

[0095] In the liquid crystal display device of the present embodimentstructured by a HDTV specification having pixels 1024×1890(rear-projection liquid crystal display device to be stated later inembodiment 4), the number of TV lines was increased in a test-charthorizontal direction by the present-embodiment peaking processingcircuit. Where the peaking processing circuit was not connected, thehorizontal number of TV lines was 600. This, however, could be increasedup to 800. Where black and white stripe bars were displayed, the whiteand black stripes could be recognized with even increased horizontaldrive frequency of up to 18 MHz.

[0096] [Embodiment 2]

[0097] In Embodiment 1, source line inversion drive was conducted withthe one-frame period of the video signal inversion period. In thepresent embodiment, device structure is the same as that ofEmbodiment 1. One example is shown wherein dot inversion drive wasconducted with one-horizontal-scanning period given for the video signalinversion period.

[0098] The dot inversion is a alternated drive method having a meritthat flicker is least conspicuous due to the polarities of video signalvoltages are in inversion between adjacent pixels.

[0099] The dot inversion drive has a characteristic that within a framethe polarities of video signal voltages to be applied are surely in aninverted relation between vertically and horizontally adjacent pixelelectrodes. Furthermore, in a next frame the pixel polarity is inverted.

[0100] Although in the present embodiment the drive voltage inversionperiod was the one-horizontal-scanning period, the inversion period mayuse a period other than this. For example, it may be atwo-horizontal-scanning period or three-horizontal-scanning period.

[0101] In the conventional example, dot inversion has required videosignal polarity inversion for each pixel. However, dot inversion driveis possible by inputting to the panel a plurality of video signals(mutually in an inverted relation) with polarities inverted everyone-horizontal-scanning period, with using a similar device structure tothat of Embodiment 1.

[0102] That is, in the present embodiment dot inversion drive isimplemented with video signals less in number of times of polarityinversions (inverted in polarity every one-horizontal-scanning period)as compared with the conventional example with polarity inversion foreach pixel. Thus, accurate alternated drive was possible improving panelreliability.

[0103] Due to this, the present embodiment can provide less-flickereddisplay high in image quality and definition as compared withEmbodiment 1. Furthermore, power consumption can be largely decreased ascompared with the conventional, similarly to Embodiment 1.

[0104] [Embodiment 3]

[0105] Although in Embodiments 1 and 2 examples using two-phase shiftregisters were shown, this embodiment demonstrates an applicationexample using one-phase shift register. FIG. 9 shows a partial circuitdiagram of a source driver circuit and pixel matrix circuit according tothe present embodiment.

[0106] In FIG. 9, 501 is a clock signal, 502 a start pulse, 503 a shiftregister, 529 a first analog video signal and 530 a second analog videosignal. Using video signals as were shown in Embodiment 1 or 2 (polarityinversion period of every frame or a one-horizontal-scanning period),the source driver circuit of FIG. 9 also can cause source line inversionor dot inversion drive. With this configuration, integration for thedrive circuits can be achieved.

[0107] [Embodiment 4]

[0108]FIG. 10A shows an outline of a projection type image display unit(rear projector) using a three-plate optical system. Numeral 600 shows amain body, numerals 603 and 604 show mirrors and numeral 605 shows ascreen. FIG. 10B shows a magnification of a portion 602 enclosed in abroken line. In the projector in this embodiment, the projection lightprojected from a light source 601 is separated into three primary colorsR, G and B by an optical system 613, and introduced through mirrors 614to three liquid crystal display panels 610 to display respective colorimages. Each of the liquid crystal display panels 610 is constituted bythin film transistors. The respective light components modulated by theliquid crystal display panels are composited by an optical system 616,being projected as a color image on the screen 605. Incidentally, 615 isa polarizing plate.

[0109] It is possible to obtain images with broad gamma-characteristicfreedom if the video signal processing circuit carries out corrections,for each color, such as liquid crystal display gamma correction, cameragamma correction, human-sight suited correction, observer's demand metcorrection, and so on. Therefore, the use of the present rear projectormakes it possible to display images preferred in balance of tone, hueand resolution.

[0110] Meanwhile, the present invention is not limited to a liquidcrystal display device integral with a driver circuit, but applicable toso-called an externally-mounted display device having a driver circuitformed on a substrate different from the liquid crystal panel.

[0111] It should be noted that the structures of the shift registercircuit, the buffer circuit, the sampling circuit, the memory circuit,for example, shown in Embodiments 1 to 3 are mere one examples. It isneedless to say that they can be suitably modified if similar functionsare provided.

[0112] Because in the present invention the video signal processingcircuit has a peaking processing circuit connected to an output of anamplifier connected to an output end of the liquid crystal panel,improvement was made for the voltage gain on the pixel electrodesreduced due to liquid panel impedance characteristics. This makes itpossible for a liquid crystal display device with increased pixels andhigh frequency drive to reduce graying image (muddy color in color) anddisplay with high definition. The present invention is effectiveparticularly for a liquid crystal display device of a high definitiontype having horizontally pixels in number of one thousand or more, suchas in HDTV, XGA or SXGA rating.

What is claimed is:
 1. A liquid crystal display device, comprising: apixel matrix area having a switching element for each pixel electrode; afirst driver circuit connected to scanning lines of said pixel matrixarea; a second driver circuit connected to signal lines of said pixelmatrix area; a video signal processing circuit for alternating videosignals and outputting a plurality of alternating current video signalsonto said first driver circuit; and a control circuit for creatingcontrol signals to control on drive to said first driver circuit, saidsecond driver circuit and said video signal processing circuit; whereinsaid video signal processing circuit includes an amplifier and a circuitfor effecting a peaking process connected to an output of saidamplifier.
 2. A liquid crystal display device according to claim 1,wherein said amplifier and said circuit for effecting the peakingprocess constitute an inversion processing circuit which outputs analternating current video signal.
 3. A liquid crystal display deviceaccording to claim 1, wherein said circuit for effecting the peakingprocess is a feedback circuit of said amplifier.
 4. A liquid crystaldisplay device according to claim 1, wherein one of said control signalsis inputted to an inversion processing circuit including said amplifierand said circuit for effecting the peaking process.
 5. A liquid crystaldisplay device, comprising: a pixel matrix area having a switchingelement for each pixel electrode; a first driver circuit connected toscanning lines of said pixel matrix area; a second driver circuitconnected to signal lines of said pixel matrix area; a video signalprocessing circuit for alternating video signals and outputting aplurality of alternating current video signals onto said first drivercircuit; and a control circuit for creating control signals to controlon drive to said first driver circuit, said second driver circuit andsaid video signal processing circuit; wherein said alternating currentsignals includes two alternating current signals in an inverted relationto each other, and wherein said video signal processing circuit includesan amplifier and a circuit for effecting a peaking process connected toan output of said amplifier.
 6. A liquid crystal display deviceaccording to claim 5, wherein said amplifier and said circuit foreffecting the peaking process constitute an inversion processing circuitwhich outputs an alternating current video signal.
 7. A liquid crystaldisplay device according to claim 5, wherein said circuit for effectingthe peaking process is a feedback circuit of said amplifier.
 8. A liquidcrystal display device according to claim 5, wherein one of said controlsignals is inputted to an inversion processing circuit including saidamplifier and said circuit for effecting the peaking process.
 9. Aliquid crystal display device according to claim 5, wherein said twoalternating current signals are respectively reversed in polarity everyone horizontal scanning period of said first driver circuit.
 10. Aprojection type image display unit comprising: a pixel matrix areahaving a switching element for each pixel electrode; a first drivercircuit connected to scanning lines of said pixel matrix area; a seconddriver circuit connected to signal lines of said pixel matrix area; avideo signal processing circuit for alternating video signals andoutputting a plurality of alternating current video signals onto saidfirst driver circuit; and a control circuit for creating control signalsto control on drive to said first driver circuit, said second drivercircuit and said video signal processing circuit; wherein said videosignal processing circuit includes an amplifier and a circuit foreffecting a peaking process connected to an output of said amplifier.11. A projection type image display unit according to claim 10, whereinsaid amplifier and said circuit for effecting the peaking processconstitute an inversion processing circuit which outputs an alternatingcurrent video signal.
 12. A projection type image display unit accordingto claim 10, wherein said circuit for effecting the peaking process is afeedback circuit of said amplifier.
 13. A projection type image displayunit according to claim 10, wherein one of said control signals isinputted to an inversion processing circuit including said amplifier andsaid circuit for effecting the peaking process.
 14. A projection typeimage display unit comprising: a pixel matrix area having a switchingelement for each pixel electrode; a first driver circuit connected toscanning lines of said pixel matrix area; a second driver circuitconnected to signal lines of said pixel matrix area; a video signalprocessing circuit for alternating video signals and outputting aplurality of alternating current video signals onto said first drivercircuit; and a control circuit for creating control signals to controlon drive to said first driver circuit, said second driver circuit andsaid video signal processing circuit; wherein said alternating currentsignals includes two alternating current signals in an inverted relationto each other, and wherein said video signal processing circuit includesan amplifier and a circuit for effecting a peaking process connected toan output of said amplifier.
 15. A projection type image display unitaccording to claim 14, wherein said amplifier and said circuit foreffecting the peaking process constitute an inversion processing circuitwhich outputs an alternating current video signal.
 16. A projection typeimage display unit according to claim 14, wherein said circuit foreffecting the peaking process is a feedback circuit of said amplifier.17. A projection type image display unit according to claim 14, whereinone of said control signals is inputted to an inversion processingcircuit including said amplifier and said circuit for effecting thepeaking process.
 18. A projection type image display unit according toclaim 14, wherein said two alternating current signals are respectivelyreversed in polarity every one horizontal scanning period of said firstdriver circuit.